1. Field of the Invention
The present invention relates to boosted power supplies of the type commonly found in a display device using a cathode ray tube (CRT), and in particular, to a circuit for generating such a boosted power supply potential using the vertical blanking signal pulses.
2. Description of the Related Art
A computer system essentially comprises a system unit housing a microprocessor, computer memory, and various other support logic, as well as various input/output (I/O) devices which are connected to the system unit and enable a user to intelligently interact with the system unit. Examples of various types of input devices include a keyboard, a mouse, a trackball, and a pen computer, as well as others. The primary output device in a computer system include a video display monitor (video monitor).
Video monitors, such as for use with digital computers, include a cathode ray tube (CRT), and driver circuitry including a video amplifier. The CRT includes three primary color cathode ray guns which are manipulated to converge on a screen that produces the color image. The three guns produce converged scanning rasters having red, green and blue fields which combine to produce white light. The typical scanning raster is a left to right horizontal and top to bottom vertical scan operated in accordance with the Video Electronics Standards Association (VESA) requirements.
A conventional monitor amplifier circuit 100 for displaying screen control states of a monitor is illustrated in FIG. 1. In general, low level color video signals blue b, red r, and green g from a video source (not shown), such as a personal computer (PC) are provided to respective video preamplifiers 101a, 101b and 101c. These preamplifiers in turn provide the respective video signals blue b, red r, and green g, via buffer amplifiers BUFF 11, BUFF12, BUFF13, to video output driver stages 103a, 103b, 103c which supply high level amplified color video signals B, R and G to respective cathode intensity control electrodes of a CRT (not shown). As can be seen, in FIG. 1, each video signal blue b, red r, and green g is applied to a respective amplifier circuit AMP11-AMP13, each of which includes four main components: a video preamplifier 101a-101c, a bias/brightness circuit 105a-105c, a video amplifier 103a-103c, and a clamp amplifier 107a-107c. Since the monitor amplifier circuits AMP11-AMP13 are identical in structure and operation, only the circuit operation of amplifier circuit AMP12 for the red video signal r will be discussed by referring to FIG. 2.
As can be seen in FIG. 2, the four main components of monitor amplifier circuit AMP12 are numbered 1-4, number 1 being bias/brightness circuit 105b, number 2 being video preamplifier 101b, number 3 being clamp amplifier 107b, and number 4 being video amplifier 103b. 
Operation of this red video channel r is as follows. Terminal 10 constitutes the red video signal input r which originates from an external source, such as a PC. Capacitor CAP12 couples the red video signal r to the noninverting input of video preamplifier 101b. 
At this point, the amplification of red video signal r is controlled by a single-throw switch SW12 and a video clamp pulse VC. In any video signal, the clamp pulses are developed just following the synchronization pulses and make it possible to restore the voltage reference level of a video signal, in this case red video signal r. This clamp pulse VC is located in the xe2x80x9cback porchxe2x80x9d of the composite red video signal r and is employed to operate switch SW12. When clamp pulse VC is high, switch SW12 is closed. Thus, each time the CRT scans a horizontal line, capacitor CAP12 will be charged to black level reference voltage VREF, which is the potential reference level of the black region of an image. This level corresponding to the black color in an image makes it possible to restore the potential reference level of the red video signal r, this level having disappeared on account of the presence of the input capacitor CAP12.
On the other hand, when video clamp pulse VC is low, switch SW12 opens and red video signal r is applied directly to video preamplifier 101b, which is shown in FIG. 2 as a unity gain amplifier. Thus, red video signal r is passed through video preamplifier 101b. 
At this point, the amplification of red video signal r is controlled by double-throw switch SW14 and signal 11. Signal 11 represents a horizontal blanking pulse that is derived from the display scanning circuits in a manner well known in video display monitors. This signal 11 is employed to operate a double-throw switch SW14 which switches the input IN12 to output buffer BUFF12, between the output of video preamplifier 101b and circuit ground. When signal 11 is high, input IN12 couples to video preamplifier 101b, the output of which is inversely amplified by video amplifier 103b to a voltage level suitable for driving a CRT and then applied to cathode electrodes of the CRT. On the other hand, when signal 11 is low, input IN12 is at circuit ground and the CRT is blanked by driving the output of the video amplifier 103b to a high level.
During operation of this amplifier circuit AMP12, output coupling capacitor CAP 22 changes the DC level at the CRT cathode. Thus, a bias clamp circuit 105b is used to restore the DC level at the CRT cathode through a series diode D11. Bias clamp circuit 105b outputs a bias clamp DC voltage which, in a typical video monitor, is usually factory set. This bias clamp voltage reinstates the charge on output capacitor CAP22 only during the blanking period. The voltage is preset, typically, in the range of 100-140 volts to compensate for differences in CRT cathode bias levels, required by each cathode in the CRT to set the black level. In addition, an adjustable voltage component of typically +/xe2x88x9210 volts may be added to this bias level to accomplish the xe2x80x98brightnessxe2x80x99 feature, such that the black level can be manually adjusted by an external source. Thus, for example, increased image brightness results when the bias clamp voltage is reduced. This results in a less positive DC bias potential at the red cathode and a related increase in image brightness.
Although the conventional monitor amplifier system 100 amplifies and conditions video signals to drive the CRT, there are several disadvantages to the circuit configuration. Referring again to FIG. 1, it can be seen that this architecture involves a significant number of interconnections. Such a low level of integration has several disadvantages. First, the circuit architecture requires a large printed circuit board (PCB), yielding higher design costs due to shielding for the radio frequency (RF) interface. Second, the conventional circuit architecture has inferior high frequency performance due to long interconnection traces between the components and due to electromagnetic interference (EMI) stemming from long signal lines and large signal swings across the video interface between each preamplifier 101a-101c and corresponding video amplifier 103a-103c. Third, the high number of interconnections require higher pin count packages which are undesirably large and expensive. Finally, the complexity of the system 100 due to the low level of integration results in longer design time.
Referring to FIG. 3, a conventional video display circuit 200a shown in more detail includes, as three of its primary integrated circuits, a pre-amplifier 202, an on-screen display (OSD) generator and pulse width modulation (PWM) circuit 204, and a CRT driver 206, interconnected substantially as shown. The pre-amplifier 202 clamps and amplifies the component blue 201b, green 201g and red 201r video signals, while providing gain and contrast control as well as the ability to introduce OSD characters. The OSD and PWM circuit 204 receives the horizontal 201h and vertical 201v blanking signals and a set 201i of control signals (based upon the well-known I2C signal standard) and in accordance therewith generates OSD character information signals 205o and gain and contrast control signals 205pa for the pre-amplifier 202.
The PWM control signals 205pa, 205pb, 205pc are filtered by a PWM filter circuit 208 to provide corresponding filtered control signals 205paf, 205pbf, 205pcf. 
The horizontal 201h and vertical 201v blanking signals are also combined in a buffer circuit 216 to produce a composite blanking signal 217 for the pre-amplifier 202.
The amplified and clamped component video signals 203b, 203g, 203r are further amplified by the CRT driver 206 to produce the higher voltage component video signals 207b, 207g, 207r needed to drive the CRT. These signals, 207b, 207g, 207r are themselves clamped using DC clamp signals 211b, 211g, 211r provided by a high voltage DC clamp circuit 210 which receives its control signals 205pbf via the PWM filter circuit 208.
The vertical blanking signal 201v is further shaped with a pulse shaper circuit 212. The resulting shaped signal 213 is clamped and buffered in a circuit 214 in accordance with a filtered control signal 205pcf to produce the drive signal 215 for the grid of the CRT.
As noted above, this circuit 200a has a number of disadvantages, including numerous interconnections between the integrated circuits. Accordingly, with reference to FIG. 4, another conventional system 200b has been used in which the output signals 227b, 227g, 227r from the CRT driver 226 are DC-coupled to the CRT. Further simplification is achieved by incorporating separate I2C interfaces for the control signals 201i within the pre-amplifier 222 and OSD generator 224 circuits. This system avoids the need for both the PWM filters 208 and the high voltage DC clamp circuit 210.
However, this circuit 200b has its own disadvantages. One disadvantage is limited adjustment range for bias clamp adjustment, brightness adjustment, and horizontal and vertical blanking. Additionally, the higher bias voltage required for the CRT driver 226 introduces some new problems. For example, the DC-coupled CRT driver 226 has a limited signal range and dissipates significantly higher power due to the high power supply voltage. Additionally, saturation and storage effects are worse due to the higher voltage processing required for such a high voltage circuit, thereby requiring more DC voltage headroom. Plus, since higher voltage devices are necessarily larger, they have more capacitance, thereby resulting in lower speed, more power and higher cost.
Referring to FIG. 5, another problem involves the need for multiple DC power supplies for biasing the CRT 270 correctly. Several electrodes within the CRT 270 require precise voltages and signals in order to ensure that the video information is displayed correctly on the screen.
A typical CRT monitor assembly 260 has component video signal amplifiers 262r, 262b, 262g, a vertical blanking amplifier 264, adjustable bias clamp circuits 266r, 266b, 266g for the component video signals, a high voltage bias supply circuit 268 and a CRT 270, all interconnected substantially as shown. The component video signals 261r, 261b, 261g are amplified by their respective amplifiers 262r, 262b, 262g. The resulting amplified video signals 263r, 263b, 263g are then AC-coupled to respective cathodes of the CRT 270. The adjustable bias clamp circuits 266r, 266b, 266g set the DC voltage level of the signals 267r, 267b, 267g driving the cathodes at the appropriate level so that a black video signal results in the appropriate cathode-to-grid potential to create a black image on the screen of the CRT 270.
Each adjustable bias clamp circuit 266r, 266b, 266g is powered via a common voltage supply 268, typically at a value of approximately 120 volts. This typically requires a power supply winding rectification and smoothing capacitor within the power supply 268 and, of course, connections from the power supply to the individual clamp circuits 266r, 266b, 266g. Such connections can create an antenna that produces radio frequency interference (RFI) due to the very high frequencies within the video amplifier circuits. To minimize this RFI, any power supply wiring connected to the video amplifiers generally require additional RFI decoupling circuits 272 at the circuit card interface, as shown.
An additional requirement in video amplifiers is a negative-going video pulse 261v to blank the screen during the vertical scan retrace interval. Typically, a pulse is taken from the vertical deflection stage, processed to form a bilevel pulse and used to drive an amplifier 264 which creates a rectangular pulse of approximately 30-40 volts peak-to-peak. This pulse is usually AC-coupled into the grid one of the CRT to ensure that the cathode-to-grid one potential is driven beyond cutoff (i.e., no light output) during the retrace interval. This blanking amplifier typically includes one or more transistors configured as a low power amplifier.
The vertical blanking amplifier 264 and the 120 volt power supply 268 add cost and components to the design of a CRT monitor. Accordingly, it would be desirable to somehow eliminate the needs for these functions, thereby reducing circuit components and costs.
A vertical blanking amplifier and bias clamp boost supply in accordance with the present invention uses the amplified vertical blanking signal to generate the boosted high voltage needed for powering the bias clamp circuits. A latch circuit is used to effectively lengthen the duration of the first vertical blanking pulse so as to ensure that the boosted power supply voltage is generated in the short time interval of one or two vertical scan intervals.
In accordance with one embodiment of the present invention, a vertical blanking circuit and bias clamp boost supply for amplifying a vertical blanking signal and generating a boosted DC voltage from the vertical blanking signal includes an amplifier circuit and a voltage restoration circuit, a voltage clamp circuit. The amplifier circuit provides an amplified vertical blanking signal with a peak-to-peak AC voltage magnitude in response to reception of an input vertical blanking signal. The voltage restoration circuit, coupled to the amplifier circuit, provides the amplified vertical blanking signal combined with a DC restoration voltage in response to reception of the amplified vertical blanking signal and the DC restoration voltage. The voltage clamp circuit, coupled to the amplifier circuit, provides a boosted DC voltage which is substantially equal to a sum of a DC clamp voltage and the peak-to-peak AC voltage magnitude in response to reception of the DC clamp voltage and the amplified vertical blanking signal.
In accordance with another embodiment of the present invention, an amplifier circuit for use in a vertical blanking circuit having a reduced startup time includes amplifier input and output terminals, a latching circuit, a current sinking circuit and a current sourcing circuit. The amplifier input terminal conveys an input vertical blanking signal. The amplifier output terminal conveys an amplified vertical blanking signal which includes an amplifier output current. The latching circuit, coupled between the amplifier input and output terminals: operates in set and cleared latch states in response to reception of the input vertical blanking signal and the amplified vertical blanking signal; and provides sink and source control signals in response to assertion of the input vertical blanking signal and in response to the operation in the set latch state. The current sinking circuit, coupled between the latching circuit and the amplifier output terminal, sinks the amplifier output current in response to the sink control signal and thereby provides a portion of the amplified vertical blanking signal. The current sourcing circuit, coupled between the latching circuit and the amplifier output terminal, sources the amplifier output current in response to the source control signal and thereby provides another portion of the amplified vertical blanking signal.
In accordance with still another embodiment of the present invention, a method for amplifying a vertical blanking signal and generating a boosted DC voltage from the vertical blanking signal includes the steps of:
receiving an input vertical blanking signal;
amplifying the input vertical blanking signal and thereby providing an amplified vertical blanking signal with a peak-to-peak AC voltage magnitude;
receiving a DC restoration voltage;
combining the amplified vertical blanking signal with the DC restoration voltage;
receiving a DC clamp voltage; and
clamping the amplified vertical blanking signal and thereby providing a boosted DC voltage which is substantially equal to a sum of the DC clamp voltage and the peak-to-peak AC voltage magnitude.
In accordance with yet another embodiment of the present invention, a method for amplifying a vertical blanking signal within a vertical blanking circuit having a reduced startup time includes the steps of:
receiving an input vertical blanking signal; and
amplifying the input vertical blanking signal and thereby providing an amplified vertical blanking signal by
operating in set and cleared latch states in response to the input vertical blanking signal and the amplified vertical blanking signal,
generating sink and source control signals in response to assertion of the input vertical blanking signal and in response to the operation in the set latch state,
sinking the amplifier output current in response to the sink control signal and thereby generating a portion of the amplified vertical blanking signal, and
sourcing the amplifier output current in response to the source control signal and thereby generating another portion of the amplified vertical blanking signal.